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High-Speed Serial Interface (HSSI) devices have become widespread in communications, from the embedded to high-performance computing systems, and from on-chip to a wide haul. Testing of H… Plus…

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Accelerating Test, Validation and Debug of High Speed Serial Interfaces
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ISBN:

9789048193974


High-Speed Serial Interface (HSSI) devices have become widespread in communications, from the embedded to high-performance computing systems, and from on-chip to a wide haul. Testing of HSSIs has been a challenging topic because of signal integrity issues, long test time and the need of expensive instruments. Accelerating Test, Validation and Debug of High Speed Serial Interfaces provides innovative test and debug approaches and detailed instructions on how to arrive to practical test of modern high-speed interfaces. Accelerating Test, Validation and Debug of High Speed Serial Interfaces first proposes a new algorithm that enables us to perform receiver test more than 1000 times faster. Then an under-sampling based transmitter test scheme is presented. The scheme can accurately extract the transmitter jitter and finish the whole transmitter test within 100ms, while the test usually takes seconds. The book also presents and external loopback-based testing scheme, where and FPGA-based BER tester and a novel jitter injection technique are proposed. These schemes can be applied to validate, test and debug HSSIs with data rate up to 12.5Gbps at a lower test cost than pure ATE solutions. In addition, the book introduces an efficieng scheme to implement high performance Gaussian noise generators, suitable for evaluating BER performance under noise conditions.

Informations détaillées sur le livre - Accelerating Test, Validation and Debug of High Speed Serial Interfaces


EAN (ISBN-13): 9789048193974
ISBN (ISBN-10): 9048193974
Version reliée
Date de parution: 2010
Editeur: Springer
250 Pages
Poids: 0,455 kg
Langue: eng/Englisch

Livre dans la base de données depuis 2007-02-07T23:03:11+01:00 (Paris)
Page de détail modifiée en dernier sur 2024-02-26T18:38:49+01:00 (Paris)
ISBN/EAN: 9789048193974

ISBN - Autres types d'écriture:
90-481-9397-4, 978-90-481-9397-4
Autres types d'écriture et termes associés:
Auteur du livre: zeljko, fan
Titre du livre: debug, interfaces, validation, test, speed four, serial, speed what you need, ever more speed

Données de l'éditeur

Auteur: Yongquan Fan; Zeljko Zilic
Titre: Accelerating Test, Validation and Debug of High Speed Serial Interfaces
Editeur: Springer; Springer Netherland
194 Pages
Date de parution: 2010-10-29
Dordrecht; NL
Imprimé / Fabriqué en
Langue: Anglais
106,99 € (DE)
109,99 € (AT)
118,00 CHF (CH)
POD
XII, 194 p.

BB; Hardcover, Softcover / Technik/Elektronik, Elektrotechnik, Nachrichtentechnik; Schaltkreise und Komponenten (Bauteile); Verstehen; Bit error rate testing; Circuit Desnign; Debugging; Electronic Design Automation; Electronic Testing; High-speed serial interfaces; Jitter injection and characterization; Mixed-signal testing; Verification & Validation; Electronic Circuits and Systems; Software Engineering; Electronics and Microelectronics, Instrumentation; System Performance and Evaluation; Software Engineering; Elektronik; Systemanalyse und -design; BC

provides innovative test and debug approaches and detailed instructions on how to arrive to practical test of modern high-speed interfaces.

first proposes a new algorithm that enables us to perform receiver test more than 1000 times faster. Then an under-sampling based transmitter test scheme is presented. The scheme can accurately extract the transmitter jitter and finish the whole transmitter test within 100ms, while the test usually takes seconds. The book also presents and external loopback-based testing scheme, where and FPGA-based BER tester and a novel jitter injection technique are proposed. These schemes can be applied to validate, test and debug HSSIs with data rate up to 12.5Gbps at a lower test cost than pure ATE solutions. In addition, the book introduces an efficieng scheme to implement high performance Gaussian noise generators, suitable for evaluating BER performance under noise conditions.

Accelerating Test, Validation and Debug of High Speed Serial Interfaces Accelerating Test, Validation and Debug of High Speed Serial Interfaces

1 Introduction. 2 Background. 3 Accelerating Receiver Jitter Tolerance Testing on ATE. 4 Transmitter Jitter Extractions on ATE. 5 Testing HSSIs with or without ATE Instruments. 6 BER Testing Under Noise. 7 Conclusions. Reference. Index.

is a Senior Test Engineer in the High Performance Analog group at Texas Instruments. He had been a Senior Staff Engineer in the Storage Peripheral Group at LSI Corporation from 2003~2008. From 1991 to 2000, he worked for Sichuan Changhong Electronic Incorporation, China. Yongquan Fan obtained his Ph.D and MENG degree from McGill University, Canada and his BS from Beijing University of Aeronautics and Astronautics, China, all in Electrical Engineering.

received his Ph. D. and M. Sc. from the University of Toronto, and his B. Eng. from University of Zagreb, Croatia. From 1996 till 1997 he worked for Lucent Microelectronics. He joined McGill University in 1998, where he is now an Associate Professor. Prof. Zilic has used a sabbatical leave in 2004/2005 to work with ST Microelectronics in Ottawa. He has received two Best Paper Awards and several honorary mentions from international conferences, as well as a national teaching award in Canada.

Yongquan Fan Zeljko Zilic

provides innovative test and debug approaches and detailed instructions on how to arrive to practical test of modern high-speed interfaces.

first proposes a new algorithm that enables us to perform receiver test more than 1000 times faster. Then an under-sampling based transmitter test scheme is presented. The scheme can accurately extract the transmitter jitter and finish the whole transmitter test within 100ms, while the test usually takes seconds. The book also presents and external loopback-based testing scheme, where and FPGA-based BER tester and a novel jitter injection technique are proposed. These schemes can be applied to validate, test and debug HSSIs with data rate up to 12.5Gbps at a lower test cost than pure ATE solutions. In addition, the book introduces an efficieng scheme to implement high performance Gaussian noise generators, suitable for evaluating BER performance under noise conditions.

Accelerating Test, Validation and Debug of High Speed Serial Interfaces Accelerating Test, Validation and Debug of High Speed Serial Interfaces
Detailed instructions on achieving practical test of modern high-speed interfaces Self-contained, with the background and tutorial included Explains statistical measures of confidence and the ways to arrive at them

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