2005, ISBN: 9780387710563
History of the Book The last three decades have witnessed an explosive development in - tegrated circuit fabrication technologies.The complexities of current CMOS circuits are reaching be… Plus…
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2005, ISBN: 9780387710563
History of the Book The last three decades have witnessed an explosive development in - tegrated circuit fabrication technologies.The complexities of current CMOS circuits are reaching be… Plus…
hive.co.uk No. 9780387710563. Frais d'envoiInstock, Despatched same working day before 3pm, zzgl. Versandkosten., Livraison non-comprise Details... |
ISBN: 9780387710563
This book details timing analysis and optimization techniques for circuits with level-sensitive memory elements. It contains a linear programming formulation applicable to the timing anal… Plus…
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ISBN: 9780387710563
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2008, ISBN: 9780387710563
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2005, ISBN: 9780387710563
History of the Book The last three decades have witnessed an explosive development in - tegrated circuit fabrication technologies.The complexities of current CMOS circuits are reaching be… Plus…
2005, ISBN: 9780387710563
History of the Book The last three decades have witnessed an explosive development in - tegrated circuit fabrication technologies.The complexities of current CMOS circuits are reaching be… Plus…
ISBN: 9780387710563
This book details timing analysis and optimization techniques for circuits with level-sensitive memory elements. It contains a linear programming formulation applicable to the timing anal… Plus…
ISBN: 9780387710563
Timing Optimization Through Clock Skew Scheduling: ab 128.49 € eBooks > Sachthemen & Ratgeber > Technik Springer-Verlag GmbH, Springer-Verlag GmbH
2008, ISBN: 9780387710563
eBooks, eBook Download (PDF), 2009, [PU: Springer US], Springer US, 2008
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Informations détaillées sur le livre - Timing Optimization Through Clock Skew Scheduling
EAN (ISBN-13): 9780387710563
ISBN (ISBN-10): 0387710566
Date de parution: 2008
Editeur: Springer US
266 Pages
Langue: eng/Englisch
Livre dans la base de données depuis 2008-09-22T15:46:09+02:00 (Paris)
Page de détail modifiée en dernier sur 2024-02-10T15:44:18+01:00 (Paris)
ISBN/EAN: 9780387710563
ISBN - Autres types d'écriture:
0-387-71056-6, 978-0-387-71056-3
Autres types d'écriture et termes associés:
Auteur du livre: friedman, eby
Titre du livre: timing, scheduling
Données de l'éditeur
Auteur: Ivan S. Kourtev; Baris Taskin; Eby G. Friedman
Titre: Timing Optimization Through Clock Skew Scheduling
Editeur: Springer; Springer US
266 Pages
Date de parution: 2008-11-16
New York; NY; US
Langue: Anglais
96,29 € (DE)
99,00 € (AT)
118,00 CHF (CH)
Available
XVI, 266 p.
EA; E107; eBook; Nonbooks, PBS / Technik/Elektronik, Elektrotechnik, Nachrichtentechnik; Schaltkreise und Komponenten (Bauteile); Verstehen; Circuit Timing; Clock Skew Scheduling; Clock Timing; Computer; EDA; Optimization; Placement Methodologies; Signal; VLSI; VLSI CAD; algorithms; automation; integrated circuit; microprocessor; programming; B; Electronic Circuits and Systems; Electrical and Electronic Engineering; Computer-Aided Engineering (CAD, CAE) and Design; Electronics and Microelectronics, Instrumentation; Engineering; Elektrotechnik; Computer-Aided Design (CAD); Elektronik; BC
VLSI Systems.- Signal Delay in VLSI Systems.- Timing Properties of Synchronous Systems.- Clock Skew Scheduling and Clock Tree Synthesis.- Clock Skew Scheduling of Level-Sensitive Circuits.- Clock Skew Scheduling for Improved Reliability.- Delay Insertion and Clock Skew Scheduling.- Practical Considerations.- Clock Skew Scheduling in Rotary Clocking Technology.- Experimental Results.Focuses on timing analysis and optimization techniques for circuits with level-sensitive memory elements Contains a linear programming formulation applicable to the timing analysis of large scale circuits Includes a delay insertion methodology that improves the efficiency of clock skew scheduling in level-sensitive circuits Provides an overview of circuit partitioning, placement, and synchronization methodologies that enables the implementation of high speed, low power circuits synchronized with ultra-modern resonant clocking technology Provides a framework for and results from implementing the described timing optimization algorithms in a parallel computing environment;
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