System Reduction for Nanoscale IC Design - nouveau livre

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Page de détail modifiée en dernier sur 2023-02-10T14:29:41+01:00 (Paris)
ISBN/EAN: 9783319072364

ISBN - Autres types d'écriture:
978-3-319-07236-4

Données de l'éditeur

Auteur: Peter Benner
Titre: Mathematics in Industry; System Reduction for Nanoscale IC Design
Editeur: Springer; Springer International Publishing
197 Pages
Date de parution: 2017-06-02
Cham; CH
Langue: Anglais
53,49 € (DE)
55,00 € (AT)
59,00 CHF (CH)
Available
XI, 197 p. 73 illus., 39 illus. in color.

EA; E107; eBook; Nonbooks, PBS / Informatik, EDV/Allgemeines, Lexika; Numerische Mathematik; Verstehen; circuit simulation; computational nanoelectronics; device simulation; model order reduction; nanoelectronics; B; Computational Science and Engineering; Mathematical Modeling and Industrial Mathematics; Electronics and Microelectronics, Instrumentation; Computer-Aided Engineering (CAD, CAE) and Design; Algorithms; Mathematical and Computational Engineering Applications; Mathematics and Statistics; Mathematische Modellierung; Mathematik für Ingenieure; Elektronik; Computer-Aided Design (CAD); Algorithmen und Datenstrukturen; BB

This book describes the computational challenges posed by the progression toward nanoscale electronic devices and increasingly short design cycles in the microelectronics industry, and proposes methods of model reduction which facilitate circuit and device simulation for specific tasks in the design cycle.

The goal is to develop and compare methods for system reduction in the design of high dimensional nanoelectronic ICs, and to test these methods in the practice of semiconductor development. Six chapters describe the challenges for numerical simulation of nanoelectronic circuits and suggest model reduction methods for constituting equations. These include linear and nonlinear differential equations tailored to circuit equations and drift diffusion equations for semiconductor devices. The performance of these methods is illustrated with numerical experiments using real-world data. Readers will benefit from an up-to-date overview of the latest model reduction methods in computational nanoelectronics.

Preface.- 1 Model order reduction of integrated circuits in electrical networks: Michael Hinze, Martin Kunkel, Ulrich Matthes, and Morten Vierling.- 2 Element-based model reduction in circuit simulation: Andreas Steinbrecher and Tatjana Stykel.- 3 Reduced Representation of Power Grid Models: Peter Benner and André Schneider.- 4 Coupling of numeric/symbolic reduction methods for generating parametrized models of nanoelectronic systems: Oliver Schmidt, Matthias Hauser, and Patrick Lang.- 5 Low-Rank Cholesky Factor Krylov Subspace Methods for Generalized Projected Lyapunov Equations: Matthias Bollhöfer and André K. Eppler.- Index.

This book describes the computational challenges posed by the progression toward nanoscale electronic devices and increasingly short design cycles in the microelectronics industry, and proposes methods of model reduction which facilitate circuit and device simulation for specific tasks in the design cycle. 

The goal is to develop and compare methods for system reduction in the design of high dimensional nanoelectronic ICs, and to test these methods in the practice of semiconductor development. Six chapters describe the challenges for numerical simulation of nanoelectronic circuits and suggest model reduction methods for constituting equations. These include linear and nonlinear differential equations tailored to circuit equations and drift diffusion equations for semiconductor devices. The performance of these methods is illustrated with numerical experiments using real-world data. Readers will benefit from an up-to-date overview of the latest model reduction methods in computational nanoelectronics.