2004, ISBN: 3639328175

Taschenbuch, [EAN: 9783639328172], VDM Verlag Dr. Müller, VDM Verlag Dr. Müller, Book, [PU: VDM Verlag Dr. Müller], VDM Verlag Dr. Müller, Bit-Serial Architecture Optimizations This work … Plus…

Taschenbuch, [EAN: 9783639328172], VDM Verlag Dr. Müller, VDM Verlag Dr. Müller, Book, [PU: VDM Verlag Dr. Müller], VDM Verlag Dr. Müller, Bit-Serial Architecture Optimizations This work presents latency optimizations for a specific hardware architecture, which was developed based on the combination of different design paradigms and thus requires sophisticated design optimizations. The architecture comprises synchronous and systematic bit-serial processing without a central controlling instance. It was patented in 2004 and targets future high-speed applications due to the abdication of long wires. So-called routers, achieving a reconfigurable system, can overcome the application specificity of the basic version of the architecture. This work focuses on the challenge of latency optimizations also covering data synchronization proble..., 63681011, Hardware, 135337011, Design & Architektur, 1322698031, Macs, 1322699031, Mainframes & Minicomputer, 63707011, Mikroprozessoren & Systemdesign, 1322697031, Netzwerke & Internet, 1322696031, Organizer & tragbare Geräte, 63705011, Parallelverarbeitende Rechner, 1322700031, PC-Einkaufsführer, 63683011, PCs, 1322701031, Peripherie, 63700011, Wartung, Reparatur & Aufrüstung, 62991011, Computer & Internet, 54071011, Genres, 52044011, Fremdsprachige Bücher<

2011, ISBN: 9783639328172

This work presents latency optimizations for a specific hardware architecture, which was developed based on the combination of different design paradigms and thus requires sophisticated d… Plus…

This work presents latency optimizations for a specific hardware architecture, which was developed based on the combination of different design paradigms and thus requires sophisticated design optimizations. The architecture comprises synchronous and systematic bit-serial processing without a central controlling instance. It was patented in 2004 and targets future high-speed applications due to the abdication of long wires. So-called routers, achieving a reconfigurable system, can overcome the application specificity of the basic version of the architecture. This work focuses on the challenge of latency optimizations also covering data synchronization problems when implementing the architecture. We propose and evaluate several variations for the realization. The latency of an evaluated IDCT implementation was reduced from 167 down to 67 clock cycles. The throughput of that implementation was improved by about 17%, while, as a side effect, area consumption was also reduced. Latency and Throughput Optimization, based on Synchronizers and Routers for a Bit-Serial Fully Pipelined Architecture Buch (fremdspr.) Taschenbuch 01.01.2011 Bücher>Fremdsprachige Bücher>Englische Bücher, VDM, .201<

ISBN: 3639328175

Edition reliée

Bit-Serial Architecture Optimizations ab 48.99 € als Taschenbuch: Latency and Throughput Optimization based on Synchronizers and Routers for a Bit-Serial Fully Pipelined Architecture. Aus… Plus…

Bit-Serial Architecture Optimizations ab 48.99 € als Taschenbuch: Latency and Throughput Optimization based on Synchronizers and Routers for a Bit-Serial Fully Pipelined Architecture. Aus dem Bereich: Bücher, English, International, Gebundene Ausgaben, Medien > Bücher, VDM Verlag<

ISBN: 3639328175

Bit-Serial Architecture Optimizations ab 48.99 EURO Latency and Throughput Optimization, based on Synchronizers and Routers for a Bit-Serial Fully Pipelined Architecture Medien > Bücher, … Plus…

Bit-Serial Architecture Optimizations ab 48.99 EURO Latency and Throughput Optimization, based on Synchronizers and Routers for a Bit-Serial Fully Pipelined Architecture Medien > Bücher, [PU: VDM Verlag Dr. Müller, Saarbrücken]<