- 5 Résultats
prix le plus bas: € 17,96, prix le plus élevé: € 181,99, prix moyen: € 50,89
1
Digital Timing Macromodeling for VLSI Design Verification (Kluwer International Series in Engineering and Computer Science. VLSI, Computer Architecture and Digital Signal Processing) - Kong, Jeong-Taek; Overhauser, David
Commander
sur ZVAB.com
€ 18,24
Envoi: € 5,791
CommanderLien sponsorisé
Kong, Jeong-Taek; Overhauser, David:

Digital Timing Macromodeling for VLSI Design Verification (Kluwer International Series in Engineering and Computer Science. VLSI, Computer Architecture and Digital Signal Processing) - Première édition

1995, ISBN: 0792395808

Edition reliée

[EAN: 9780792395805], Gebraucht, sehr guter Zustand, [SC: 5.79], [PU: Kluwer Academic Publishers, Norwell, Massachusetts, U.S.A.], White hardcover with white lettering on spine and upper … Plus…

NOT NEW BOOK. Frais d'envoi EUR 5.79 PsychoBabel & Skoob Books, Didcot, Oxfordshire, OXON, United Kingdom [2917279] [Rating: 5 (von 5)]
2
Commander
sur ZVAB.com
€ 17,96
Envoi: € 5,701
CommanderLien sponsorisé

Kong, Jeong-Taek; Overhauser, David:

Digital Timing Macromodeling for VLSI Design Verification (Kluwer International Series in Engineering and Computer Science. VLSI, Computer Architecture and Digital Signal Processing) - Première édition

1995, ISBN: 0792395808

Edition reliée

[EAN: 9780792395805], D'occasion, très bon état, [SC: 5.7], [PU: Kluwer Academic Publishers, Norwell, Massachusetts, U.S.A.], White hardcover with white lettering on spine and upper board… Plus…

NOT NEW BOOK. Frais d'envoi EUR 5.70 PsychoBabel & Skoob Books, Didcot, Oxfordshire, OXON, United Kingdom [2917279] [Note: 5 (sur 5)]
3
Commander
sur AbeBooks.de
€ 18,24
Envoi: € 5,791
CommanderLien sponsorisé
Kong, Jeong-Taek; Overhauser, David:
Digital Timing Macromodeling for VLSI Design Verification (Kluwer International Series in Engineering and Computer Science. VLSI, Computer Architecture and Digital Signal Processing) - Première édition

1995

ISBN: 0792395808

Edition reliée

[EAN: 9780792395805], Gebraucht, sehr guter Zustand, [PU: Kluwer Academic Publishers, Norwell, Massachusetts, U.S.A.], White hardcover with white lettering on spine and upper board and co… Plus…

NOT NEW BOOK. Frais d'envoi EUR 5.79 PsychoBabel & Skoob Books, Didcot, Oxfordshire, OXON, United Kingdom [2917279] [Rating: 5 (von 5)]
4
Commander
sur Biblio.co.uk
$ 18,01
(environ € 18,02)
Envoi: € 5,891
CommanderLien sponsorisé
Kong, Jeong-Taek; Overhauser, David:
Digital Timing Macromodeling for VLSI Design Verification (Kluwer International Series in Engineering and Computer Science. VLSI, Computer Architecture and Digital Signal Processing) - edition reliée, livre de poche

1995, ISBN: 9780792395805

Norwell, Massachusetts, U.S.A.: Kluwer Academic Publishers, 1995. White hardcover with white lettering on spine and upper board and contents in very good clean condition, showing minimal … Plus…

Frais d'envoi EUR 5.89 PsychoBabel & Skoob Books
5
Digital Timing Macromodeling for VLSI Design Verification - Jeong-Taek Kong/ David V. Overhauser
Commander
sur Hugendubel.de
€ 181,99
Envoi: € 0,001
CommanderLien sponsorisé
Jeong-Taek Kong/ David V. Overhauser:
Digital Timing Macromodeling for VLSI Design Verification - edition reliée, livre de poche

ISBN: 0792395808

Digital Timing Macromodeling for VLSI Design Verification ab 181.99 € als gebundene Ausgabe: Auflage 1995. Aus dem Bereich: Bücher, Wissenschaft, Technik, Medien > Bücher, Springer US

Nr. 4061883. Frais d'envoi, , DE. (EUR 0.00)

1Comme certaines plateformes ne transmettent pas les conditions d'expédition et que celles-ci peuvent dépendre du pays de livraison, du prix d'achat, du poids et de la taille de l'article, d'une éventuelle adhésion de la plateforme, d'une livraison directe par la plateforme ou via un prestataire tiers (Marketplace), etc. il est possible que les frais de livraison indiqués par eurolivre ne correspondent pas à ceux de la plateforme qui propose l'article.

Données bibliographiques du meilleur livre correspondant

Détails sur le livre
Digital Timing Macromodeling for VLSI Design Verification

Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques.

Informations détaillées sur le livre - Digital Timing Macromodeling for VLSI Design Verification


EAN (ISBN-13): 9780792395805
ISBN (ISBN-10): 0792395808
Version reliée
Date de parution: 1995
Editeur: Springer-Verlag GmbH
292 Pages
Poids: 0,602 kg
Langue: eng/Englisch

Livre dans la base de données depuis 2007-10-21T19:40:29+02:00 (Paris)
Page de détail modifiée en dernier sur 2023-10-27T21:27:12+02:00 (Paris)
ISBN/EAN: 0792395808

ISBN - Autres types d'écriture:
0-7923-9580-8, 978-0-7923-9580-5
Autres types d'écriture et termes associés:
Auteur du livre: jeong, kong, overhaus
Titre du livre: engineering design, digital timing macromodeling for vlsi design verification, digital design and computer architecture, design and the computer, architecture science


Données de l'éditeur

Auteur: Jeong-Taek Kong; David V. Overhauser
Titre: The Springer International Series in Engineering and Computer Science; Digital Timing Macromodeling for VLSI Design Verification
Editeur: Springer; Springer US
265 Pages
Date de parution: 1995-05-31
New York; NY; US
Langue: Anglais
160,49 € (DE)
164,99 € (AT)
177,00 CHF (CH)
Available
XXI, 265 p.

BB; Hardcover, Softcover / Technik/Elektronik, Elektrotechnik, Nachrichtentechnik; Schaltkreise und Komponenten (Bauteile); Verstehen; Modulation; VLSI; computer-aided design (CAD); design; development; history; integrated circuit; interconnect; model; modeling; simulation; tables; transistor; transmission; verification; Electronic Circuits and Systems; Computer-Aided Engineering (CAD, CAE) and Design; Electrical and Electronic Engineering; Computer-Aided Design (CAD); Elektrotechnik; BC

1 Introduction.- 1.1 Overview of the VLSI Design and Verification Process.- 1.2 Problems in MOS Digital Macromodeling.- 1.3 Contributions of The New Macromodel.- 2 Survey of Simulation and Macromodeling Techniques.- 2.1 Introduction.- 2.2 Circuit Simulation.- 2.3 Macromodeling.- 2.4 Gate-level and Switch-level Simulation.- 2.5 Switch-level Timing Simulation.- 2.6 Fast-timing Simulation.- 2.7 Interconnection Analysis.- 2.8 Mixed-mode/Mixed-domain Simulation.- 3 A Nonlinear Macromodel.- 3.1 Introduction.- 3.2 A Macromodel for the General Case.- 3.3 Macromodeling with Fast Input Transitions.- 3.4 Slow Input and Fast Output Transitions.- 3.5 Experimental Results.- 4 Reduction Techniques for Complex Gates.- 4.1 Introduction.- 4.2 Reduction of Series-connected Transistors.- 4.3 Generalized Reduction Techniques for Complex Gates.- 4.4 Experimental Results.- 5 Accounting for RC-Interconnects.- 5.1 Introduction.- 5.2 Related Work.- 5.3 RC-interconnect Effects.- 5.4 Modeling the Effective Driver-loading.- 5.5 Driver Output Waveform Estimation.- 5.6 Experimental Results.- 6 Transmission Gate Modeling.- 6.1 Introduction.- 6.2 A Gate Driving a Transmission Gate.- 7 Conclusions.- 7.1 Summary.- 7.2 Future Research.- A The Spice Level 2 Model.- B Nonlinear Macromodel Output Response Derivations.- B.1 The Derivation of the Output Response in Region III.- B.2 The Derivation of the Output Response in Region VI.- D Delay Errors for Various AOI Gates.- References.

< pour archiver...